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Stijn Ringeling is a PhD candidate in the Emerging technologies Lab, which is part of the Integrated Circuits group. He is working on the RAISE project, where his main aim is to develop faster evaluation techniques for circuit performance simulations using Machine Learning. Besides his research, Stijn is also involved as a TA for the 5CCA0 course and is supporting various Bachelor students for their thesis projects.

Stijn received his Bachelor and Master degrees from the Eindhoven University of Technology in the Netherlands, in 2019 and 2021, respectively. He started as a PhD candidate at Eindhoven University of Technology in September 2021. His main interests are in the field of Machine Learning applied to the simulations performed on integrated circuits.