ºÚÁϸ£ÀûÍø

Mismatch in size

At the moment, electronic chips and photonic chips are each made in different factories, with different production methods, and on different sizes of wafers. For example: many high-performance photonic chips, especially those requiring native light sources and amplifiers, rely on indium phosphide and gallium arsenide technologies, which typically use 100 to 150 mm (4 to 6 inch) wafers, whereas mainstream electronics is predominantly silicon based and wafers usually are about 200 to 300 mm (8 to 12 inch) in size. Jiao: ‘By scaling up photonic manufacturing to similar wafer sizes, we can make use of established lithography and other production processes from the mature electronics industry.’

What’s more, current solutions for building interfaces between electronics and photonics consume a lot of energy. Jiao: ‘Industry nowadays is not only calling for high speed, terabits per second chips, but also demands energy efficiency. The target energy consumption per transmitted bit is moving toward the femtojoule-per-bit regime. When it comes to semiconductors, energy consumption is becoming as important as speed.’

Three concepts

Jiao is working on three different concepts to combine electronics and photonics on a single chip. The first is direct bonding at the wafer level. ‘For this technology to work, photonic and electronic layouts need to be co-designed so that the bonded wafers and the subsequent interconnects can be aligned with high precision.’ Wafer bonding is one of the key routes for heterogeneous integration, because it can combine dissimilar material platforms at wafer scale. It is especially attractive when high alignment accuracy, dense integration and manufacturability are important. Depending on the materials, wafer sizes and process flow, different bonding schemes can be used to integrate photonics and electronics. However, wafer bonding becomes less straightforward when the source and target platforms use very different wafer sizes, as is often the case for indium phosphide and silicon.

Stamping chiplets

Together with companies like and , Jiao has been working on a microtransfer printing technique, where small photonic chiplets from a source wafer are essentially stamped on top of a target electronic or photonic wafer. ‘We have demonstrated that this works well in the case of stamping individual indium phosphide chiplets onto a silicon nitride wafer. In a follow-up project, we are scaling up this technology to print entire arrays of chiplets in a single step, with a new semi-automated transfer tool to be installed in our own cleanroom. In that funded project, we are pursuing a variety of applications, ranging from a high-speed transceiver for 6G to a single photon detector for quantum computing purposes.’  

Fitting Lego onto Duplo

In a third line of research, Jiao is exploring an entirely new approach. ‘We are growing indium phosphide layers directly on top of silicon-based substrates.’ The crystal structures and dimensions of these respective materials are very different, which makes direct growth extremely challenging. That is like trying to build Lego blocks on top of Duplo. Technically it is called lattice mismatch. ‘Most researchers use a rather thick transition buffer layer to overcome the mechanical stress introduced by the lattice mismatch, but that dramatically hinders the communication between the two layers of materials. An alternative method is to carve wedges into the silicon layer, and grow the indium phosphide inside the resulting grooves. However, the size and scalability of the indium phosphide material is limited by the size of the grooves. ‘Together with the French company , we are exploring a new and more scalable and manufacturable technology. The key is to create a thin indium phosphide membrane on silicon across the entire wafer surface. This provides a new starting platform for subsequent growth of complex functional photonic structures. The most severe lattice-mismatch bottleneck is thus addressed at the platform level.’ The first success has already been achieved; In the NanoLabTUe cleanroom, Jiao and his team managed to grow uniform layers of indium phosphide on top of a 100 mm silicon wafer. Growth on 150 mm and 200 mm silicon wafers have also been reported by other European industrial partners.

‘Ten years ago, I decided to focus on a topic that has since become increasingly relevant,’ Jiao says with satisfaction. ‘Achieving this type of integration is very challenging. It allows me to do curiosity driven, groundbreaking research, and at the same time, industry is really keen for it. Around the world, there is a strong investment in new datacenters with about one new datacenter being built every 2-3 days. All of these demand faster and more energy-efficient chip technologies. It is very stimulating to experience that there is clearly a need for the technology I am developing.’

Tailor-made technology

The researcher expects that in the future, we will see different combinations of semiconductor technologies for different applications. ‘For many digital applications, silicon remains the natural platform. For high-speed analogue, optoelectronics and mixed-signal applications, indium phosphide can offer important performance advantages. For example, in very high-frequency applications, it can be advantageous to realize both the electronic driver and the photonic device in indium phosphide, because that allows tight co-integration with minimal performance compromise.’ Motivated by this, Jiao and his team also started a new research line to enable in-house  indium phosphide transistor technology under the roof of the NanoLabTUe cleanroom.